1. Field of the Invention
The present invention relates to a switch circuit device having less leakage current.
2. Description of the Background Art
In recent years, an IC has been further miniaturized so as to increase the packaging density of a high-frequency circuit and a whole circuit. Such an IC includes a number of switch circuit devices, and these switch circuit devices are formed of a MOSFET (s). Conventionally, the switch circuit device is formed of a single MOSFET or a pair of an n-ch MOSFET and a p-ch MOSFET (called a transfer gate). Here, as the IC is further miniaturized, the power supply voltage and the threshold voltage of the MOSFET are decreased. Therefore, insertion loss when the switch circuit device is in the conduction state (hereinafter referred to as ON) increases, and also, isolation characteristics when the switch circuit device is in the current interrupt state (hereinafter referred to as OFF) are deteriorated.
Japanese Laid-Open Patent Publication No. 11-163647 discloses a switch circuit device which solves such a problem. FIG. 23 is a diagram showing a configuration of the conventional switch circuit device of Japanese Laid-Open Patent Publication No. 11-163647. In the switch circuit device of FIG. 23, leakage current is reduced by changing the back gate potential of a MOSFET between when the MOSFET is ON and when the MOSFET is OFF.
Japanese Laid-Open Patent Publication No. 2005-515657 and Hiroshi Kawaguchi, Koichi Nose and Takayasu Sakurai, “A Super Cut-Off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage”, JSSC, vol. 35, no. 10, p. 1498-1501, October 2000 (hereinafter referred to as Document 1) describe switch circuit devices. FIGS. 24 and 25 are diagrams showing configurations of the conventional switch circuit devices described in Japanese Laid-Open Patent Publication No. 2005-515657 and Document 1, respectively. In the switch circuit devices of FIGS. 24 and 25, three MOSFETs are connected in series so that leakage current is reduced.
Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi and Takayasu Sakurai, “Managing Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T-Switch (AT-Switch) and Super Cut-off CMOS”, VLSI Symposia Circuit 8-3, June 2005 (hereinafter referred to as Document 2) also describes a switch circuit device. FIG. 26 is a diagram showing a configuration of the conventional switch circuit device of Document 2. In the switch circuit device of FIG. 26, three MOSFETs are connected into a T-shape, and a voltage of Vdd/2 is applied to a connection point between two MOSFETs connected in series when the switch circuit device is OFF, thereby improving the isolation characteristics of the switch circuit device. This is achieved by utilizing characteristics that leakage current between the drain and the source of an n-ch MOSFET decreases with an increase in the drain (or source) potential of the n-ch MOSFET when the n-ch MOSFET is OFF and characteristics that leakage current between the drain and the source of a p-ch MOSFET decreases with a decrease in the drain (or source) potential of the p-ch MOSFET when the p-ch MOSFET is OFF.
However, the above-described conventional switch circuit devices have the following problems. In the switch circuit device of FIG. 23, since the switch circuit device is formed of MOSFETs any two or more of which are not connected in series, the effect of improving isolation characteristics when the switch circuit device is OFF is small.
The switch circuit devices of FIGS. 24 and 25 require three MOSFETs connected in series. As each of the MOSFETs connected in series, a MOSFET having a large size is used so as to reduce the insertion loss of the switch circuit device when it is ON. As a result, the footprint in a chip of the MOSFETs connected in series is large.
In the switch circuit device of FIG. 26, when the switch circuit device is OFF, the two MOSFETs connected in series are OFF, and a voltage of Vdd/2 is applied via the drain of the MOSFET connected in parallel to the drains of the MOSFET connected in series. On the other hand, when the switch circuit device is ON, the MOSFET connected in parallel is OFF, and a voltage of Vdd/2 is applied to the drain of the MOSFET connected in parallel. In other word, a constant voltage of Vdd/2 is applied to the drain of the MOSFET connected in parallel no matter whether the switch circuit device is ON or OFF. Therefore, when the switch circuit device is OFF, the OFF-state isolation characteristics are not satisfactorily improved. Also, when the switch circuit device is ON, the isolation characteristics of the MOSFET connected in parallel are deteriorated, resulting in an increase in the insertion loss of the switch circuit device.